CS303 Digital Design

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Course Code Course Title Weekly Hours* ECTS Weekly Class Schedule
T P
CS303 Digital Design 3 2 6
Prerequisite None It is a prerequisite to
CS309
EE436
Lecturer Mohammad Al Samman Office Hours / Room / Phone
Monday:
14:00-16:00
Wednesday:
14:00-16:00
Friday:
10:00-12:00
A F2.7 - 033 957 223
E-mail malsamman@ius.edu.ba
Assistant Assistant E-mail
Course Objectives To introduce the main building blocks of digital circuits and develop the skills of the students in the area of logic design and digital systems
Textbook R1: Digital Design, Morris M. Mano, Michael D. Ciletti, Pearson (5th Ed.) R2: Fundamentals of digital logic with VHDL design, Stephen Brown, Zvonko Vranesic, McGraw Hill (3rd Ed.)
Additional Literature
  • 1. Digital Design Using VHDL A System Approach, William J. Dally, R. Curtis Harting, Tor M. Aamodt, Cambridge University Press, 2015
  • 2. Digital Design and Computer Architecture, David Harris and Sarah Harris, Elsevir, 2013
Learning Outcomes After successful  completion of the course, the student will be able to:
  1. Express, convert and calculate with real numbers having different bases
  2. Analyse and optimize digital system with respect to number and type of logical gates
  3. Design and test digital circuits, configured into functional systems in programmable devices using VHDL
  4. Understand architecture and timing diagrams of digital circuits that include memory blocks (RAM)
  5. Write a report that clearly and concisely explains the results obtained in laboratory exercises
Teaching Methods Class discussions with examples. Active tutorial sessions for engaged learning and continuous feedback on progress. Assignments and laboratory exercises that involve work with commercial programmable logic circuits.
Teaching Method Delivery Face-to-face Teaching Method Delivery Notes
WEEK TOPIC REFERENCE
Week 1 Introduction R1: Ch1
Week 2 Introduction, Digital Systems and Binary Numbers R1: Ch1
Week 3 Boolean Algebra and Logic Gates R1: Ch2
Week 4 Gate-Level Minimization R1: Ch3
Week 5 Gate-Level Minimization R1: Ch3
Week 6 Combinational Logic R1: Ch4
Week 7 Combinational Logic R1: Ch4
Week 8 MIDTERM EXAM --
Week 9 Combinational Logic R1: Ch4
Week 10 Synchronous Sequential Logic R1: Ch5
Week 11 Synchronous Sequential Logic R1: Ch5
Week 12 Synchronous Sequential Logic R1: Ch5
Week 13 Registers and Counters R1: Ch6
Week 14 Registers and Counters R1: Ch6
Week 15 General Revision --
Assessment Methods and Criteria Evaluation Tool Quantity Weight Alignment with LOs
Final Exam 1 40
Semester Evaluation Components
Quizzes 5 20
Midterm exam 1 20
Laboratory/Simulation Assignments 10 20
***     ECTS Credit Calculation     ***
 Activity Hours Weeks Student Workload Hours Activity Hours Weeks Student Workload Hours
Lecture Hours 3 14 42 Assignments 1 10 10
Lab & Reporting 4 10 40 Home Study 1 13 13
In-term Exam Study 15 1 15 Final Exam Study 15 2 30
        Total Workload Hours = 150
*T= Teaching, P= Practice ECTS Credit = 6
Course Academic Quality Assurance: Semester Student Survey Last Update Date: 08/04/2024
QR Code for https://ecampus.ius.edu.ba/syllabus/cs303-digital-design

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